Test data compression based on geometric shapes

The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and efficient testindependent compression technique based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The test set is partitioned into blocks and then each block is encoded separately. The encoder has the choice of encoding either the 0’s or the 1’s in a block. In addition, it encodes a block that contains only 0’s (or 1’s) and x’s with only 3 bits. Furthermore, if the cost of encoding a block using geometric shapes is higher than the original cost of the block, the block is stored as is without encoding. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest full-scanned versions of ISCAS89 benchmark circuits. The proposed technique achieves significantly higher compression in comparison to other test-independent compression techniques reported in the literature. Test data decompression is performed on chip and is performed either in hardware using a decoding circuitry or in software using an embedded processor on chip. We explored both options and reported the cycle count required for test data decompression using an embedded processor and using a hardware decoder.